Flash memory has become increasingly popular in recent years. A typical flash memory includes a memory array having a large number of memory cells arranged in blocks. One of the most commonly known flash memories is the one-transistor flash memory, wherein each of the memory cells is fabricated as a field-effect transistor having a control gate and a floating gate. The floating gate is capable of holding charges, and is separated from source and drain regions contained in a substrate by a layer of thin oxide (tunneling oxide). Each of the memory cells can be electrically charged by injecting electrons from the drain region through the tunneling oxide layer into the floating gate. The charges can be removed from the floating gate by tunneling the electrons to the substrate through the tunneling oxide layer. The data stored in a memory cell is determined by the presence or absence of charges in the floating gate.
It is highly desirable to scale down write/erase voltages of flash memories, which has typically been achieved by decreasing the thickness of the tunneling oxide layers. One method for reducing the thickness of the tunneling oxide layer without causing severe charge loss is using a (poly-)Si—SiO2—SiN—SiO2—Si (SONOS) structure. FIG. 1 illustrates a conventional SONOS flash memory cell. Tunneling oxide layer 2 is formed on silicon substrate 10. Silicon nitride layer (floating gate) 4 is formed on tunneling oxide layer 2, and has local traps for trapping and storing charges. Blocking oxide layer 6 is formed on floating gate 4 to prevent leaked charges from reaching gate electrode 8, which is typically formed of polysilicon.
In conventional SONOS memory cells, charges are stored inside the discrete and electrically isolated traps of nitride (SiN), while only the trapped charges close to the oxide defects can leak out. The good electrical isolation differs a SONOS memory cell from a conventional memory cell having a continuous polysilicon floating gate, which may have all stored charges leak out through a defect in the tunneling oxide layer. Therefore, it is possible to significantly scale down the thickness of the tunneling oxide layer 2 of a SONO memory cell, for example, to between about 2 nm and about 2.5 nm, while the charge retention ability of the SONO memory cell is not noticeably compromised. In addition, with the reduction of the thickness of the tunneling oxide layer, write/erase voltages can be lowered.
Although the SONOS memory devices provide a potential solution for down-scaling the tunneling oxide layer below that of a conventional memory device with a poly floating gate, it is still challenging to scale down the write/erase voltage and maintain the required ten-year data retention. This is caused by the conflicting requirements for write/erase the flash memory cells and retaining data stored in the flash memory cells. For example, to reduce the leakage of the stored charges, blocking oxide layer 6 and tunneling oxide layer 2 preferably have great thicknesses. However, increasing the thicknesses of blocking oxide 6 and tunneling oxide 2 requires the write/erase voltage to be increased. New flash memory cells having good data retaining ability while at the same time with reduced write/erase voltages are thus needed.